1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising a memory core having memory cells, and more particularly to a semiconductor integrated circuit which operates its memory core in accordance with commands supplied from exterior.
The present invention also relates to a semiconductor integrated circuit comprising a plurality of banks each having a memory core and a control circuit thereof.
Moreover, the present invention relates to a semiconductor integrated circuit which operates its memory core in synchronization with a clock signal.
2. Description of the Related Art
Owing to the development of semiconductor manufacturing technologies, semiconductor integrated circuits have been increasing its operation speed. Microcomputers and the like have improved in operating frequency year by year, with a growing disparity from the operating frequencies of DRAMs and other semiconductor memories. To narrow this disparity, there have been developed high-speed memories including SDRAMs (Synchronous DRAMs) and FCRAMs (Fast Cycle RAMs). Such memories as an SDRAM perform read operations, write operations, refresh operations, or the like depending on commands supplied from exterior.
FIG. 1 shows an example of the major part of a conventional SDRAM.
The SDRAM has an input buffer 1 for receiving a command signal CMD from exterior, a command decoder 2 for decoding the command signal CMD to generate a command control signal CMDCON, and banks BK0, BK1, BK2, and BK3 each including a control circuit 3 and a memory core 4. The memory core 4 has a plurality of not-shown memory cells, word decoders, sense amplifiers, precharging circuits, and the like.
The control circuit 3 receives a plurality of command signals CMDCON from the command decoder 2, and outputs a plurality of timing signals TIM for controlling the memory core 4 in accordance with these control signals CMDCON. The control circuit 3 has timing signal generators 3a each of which generates a timing signal TIM, decision circuits 3b for controlling the operations of predetermined timing generators 3a in accordance with the operating state of the memory core 4, and internal control circuits 3c for controlling timing signal generators 3a and decision circuits 3b. Each of the decision circuits 3b has the function of disabling the acceptance of a new command control signal CMDCON during the operations of the timing signal generators 3a which are controlled by themselves. Here, the commands to be acceptance-disabled are generally referred to as illegal commands. For example, a decision circuit 3b that controls a timing signal generator 3a associated with a read operation disables the acceptance of read commands while this timing signal generator 3a is in operation. In this case, illegal commands are the read commands supplied during the read operation.
The description as to which command is considered as an illegal command in what operating state is given in SDRAM data sheets or the like. Therefore, illegal commands will not be supplied to the SDRAM in normal operations. To avoid malfunctions due to accidental supply of illegal commands, the decision circuits 3b control the timing signal generators 3a. 
In the control circuits 3 described above, the decision circuits 3b are respectively formed for each of the timing signal generators 3a, and these decision circuits 3b individually determining illegal commands based on the actual operations of the timing signal generators 3a so that malfunctions are prevented. The control circuits 3 have many timing signal generators 3a aside from those shown in the diagram, and there are a number of combinations of operating states for illegal commands. Accordingly, it is not easy to form the decision circuits 3b with consideration taken into all the combinations. In addition, forming a number of decision circuits 3b contributes to an increase in chip size.
Besides, as in the SDRAM shown in FIG. 1, it is more complicated to determine illegal commands in SDRAMs having a plurality of banks. For example, a read command supplied to the same bank during a read operation is considered as an illegal command, yet as a normal command (legal command) to other banks. Accordingly, the control circuits 3 are conventionally formed in the individual banks BK0-BK3 so as to individually determine illegal commands.
Furthermore, in case command specifications are modified or a new function is added at the time of development of new products, it is required to consider the combinations of operating states for illegal commands. This consequently increases design man-hours because the conventional control circuits 3 can not be simply utilized.
An object of the present invention is to provide a semiconductor integrated circuit capable of determining commands as illegal with facility and reliability.
According to one of the aspects of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has a memory core having a plurality of memory cells, a command decoder, a mask circuit, and a control circuit. The command decoder decodes a command signal to generate a command control signal. The mask circuit receives the command control signal to recognize the operating state of the memory core thereafter, and activates a mask signal when the command signal to be supplied anew is unacceptable. That is, the mask circuit recognizes the operations of the control circuit and memory core not from the operating state of the control circuit but from the supplied command signal. The control circuit disables an operation of the memory core corresponding to the command control signal when the mask signal is activated.
Illegal commands are decided by the mask circuit alone. On this account, the control circuit need not be provided with a circuit for individually determining commands as illegal in accordance with actual operating states. Therefore, using the mask circuit makes it possible to prevent malfunctions resulting from illegal commands with facility and reliability. The intrinsic functions of the control circuit have only to be verified at the time of design and circuit modifications, which results in improving design efficiency.
According to another aspect of the semiconductor integrated circuit in the present invention, the control circuit has an input circuit. The input circuit receives the command control signal and the mask signal and disables the acceptance of the command control signal when the mask signal is activated. That is, the input circuit discriminates between acceptable commands and unacceptable commands. Accordingly, illegal commands can be controlled at the entrance of the control circuit, allowing simpler configuration of the control circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the control circuit and the memory core individually operate in synchronization with a clock signal. The mask circuit activates the mask signal based on the number of clocks in the clock signal. Therefore, the mask signal is generated at precise timing particularly in the semiconductor integrated circuit of clock synchronous type.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a plurality of banks each having the memory core and the control circuit. Each mask circuit receives the command control signal and a bank selecting signal to individually recognize the operating state of the memory core in each of the banks thereafter. Then, the mask circuit activates the mask signal corresponding to the control circuit in a predetermined bank when a command signal to be supplied anew to the bank is unacceptable.
Therefore, even in the semiconductor integrated circuit having a plurality of banks, circuits for individually determining commands as illegal in accordance with the actual operating states need not be formed in the control circuit in each of the banks. Using the mask circuit prevents malfunctions resulting from illegal commands with facility and reliability.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has an interleaving function of performing a read operation or a write operation in sequence on a plurality of the banks with consecutive addresses when a burst length, or the number of times the read operation or the write operation is performed in succession, is greater than a predetermined value. Even in the semiconductor integrated circuit having the interleaving function, malfunctions due to the illegal commands can be prevented with facility and reliability by deciding illegal commands by the mask circuit.